Analog Layout Design, Staff Engineer in Hanoi
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custom_fields.SubCategory-Layout-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2027-01-31 custom_fields.Multikeywordfacets-Hardware">Join our Talent Community! .Find Jobs ForWhere? Search JobsAnalog Layout Design, Staff Engineer in HanoiHanoi, Hanoi, VietnamEngineeringEmployeeSave Job ShareJump toOverviewOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.Play VideoJob DescriptionCategory Engineering Hire Type Employee Job ID 13915 Remote Eligible No Date Posted 01/01/2026Alternate Job Titles:
- Analog Layout Staff Engineer
- Analog IC Layout Staff Engineer
- Custom Layout Staff Engineer
- Working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
- Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
- Applying Analog Layout techniques to ensure design meets performance with minimum area and good yield.
- Building and enhancing layout flow for faster, higher quality design processes.
- Performing layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
- Conducting PERC verification for ESD/LUP checks.
- Completing all design quality checks and data quality checks.
- Collaborating with Place and Route engineers to integrate analog layouts into the top level.
- Working with the Package team to ensure the integration of top die and package.
- Participating in design reviews across the global team.
- Engaging in package design, including interposer and RDL design.
- Collaborating closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
- Joining research programs to implement new ideas for future products and flows.
- Leading a layout team to complete a full design block.
- Mentoring junior layout engineers or interns.
- Driving the development of high-performance Analog IPs that power cutting-edge technologies.
- Enhancing the layout design process for improved efficiency and quality.
- Ensuring the robustness and reliability of our designs through meticulous verification processes.
- Contributing to the integration of complex layouts into top-level designs.
- Fostering collaboration and knowledge sharing across global teams.
- Mentoring and developing the next generation of layout engineers.
- BS in Electronics Engineering, Electromechanics, Telecommunications.
- 5+ years of experience in custom layout.
- Proficiency with layout entry tools: Cadence, Synopsys.
- Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
- Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
- Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
- Experience mentoring/leading junior layout engineers.
- Ability to write layout review presentations and layout verification reports.
- Good English communication skills.