Staff Memory Layout Engineer in Da Nang
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custom_fields.SubCategory-Layout-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2027-02-28 custom_fields.Multikeywordfacets-Hardware">Join our Talent Community! .Find Jobs ForWhere? Search JobsStaff Memory Layout Engineer in Da NangDa Nang, Da Nang, VietnamEngineeringEmployeeSave Job ShareJump toOverviewOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.Play VideoJob DescriptionDate posted 02/04/2026Category Engineering Hire Type Employee Job ID 15068 Remote Eligible No Date Posted 02/04/2026Alternate Job Titles:
- Staff Memory Layout Engineer
- Lead the physical layout design of advanced memory IP (SRAM, ROM,eDRAM, etc.) at cell, array, and peripheral levels
- Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints
- Optimizelayouts for area, performance, power, yield, and manufacturability
- Perform RC extraction, parasitic analysis, and signal integrity verification for dense memory arrays
- Debug and resolve LVS/DRC and memory-specific issues efficiently
- Work cross-functionally with circuit, verification, and process teams to deliver first-pass silicon success
- Addressing reliability concerns (EM, IR drop, soft errors) in layouts
- Mentoring junior engineers and sharing best practices
- Delivering robust, high-performance memory IP for top tech companies
- Reducing risk and time-to-market with first-pass silicon success
- Driving innovation in layout methodologies and automation
- Elevating team capability and quality
- Supporting Synopsys' leadership in memory IP
- Empowering customers' innovation in AI and advanced systems
- Bachelor's orMaster'sdegreein Electronics Engineering, Telecommunication, Physics, or related fields.
- Minimum of 5 years of experience in layout design.
- Deep memory layout knowledge (SRAM, ROM,eDRAM, etc.)
- Proficiencywith Custom Compiler, IC Compiler, Virtuoso
- Understanding of process rules, DRC/LVS, and memory constraints
- Experience with RC extraction, parasitic reduction, and signal integrity
- Ability to debug andoptimizeformanufacturability and reliability
- Detail-oriented and analytical
- Collaborative and communicative
- Innovative and proactive
- Supportive mentor and team player