Analog Design, Sr Supervisor
Synopsys Xem tất cả việc làm
- Tp Hồ Chí Minh
- Lâu dài
- Toàn thời gian
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custom_fields.CareerAreas-Analog-Design custom_fields.SubCategory-Analog-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2027-02-28 custom_fields.Multikeywordfacets-Hardware">Join our Talent Community! .Find Jobs ForWhere? Search JobsAnalog Design, Sr SupervisorHo Chi Minh City, Ho Chi Minh, VietnamEngineeringEmployeeSave Job ShareJump toOverviewOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.Play VideoJob DescriptionDate posted 02/26/2026Category Engineering Hire Type Employee Job ID 15458 Remote Eligible No Date Posted 02/26/2026Alternate Job Titles:
- Senior AMS Timing Supervisor
- Analog Mixed Signal Design Lead
- Timing Model Design Manager
- Develop accurate timing models for macros used in multi-die designs.
- Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
- Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
- Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
- Perform STA (Static Timing Analysis) using industry-standard EDA tools.
- Support constraint development and validation for timing sign-off.
- Collaborate with design, verification, and physical implementation teams to resolve timing issues.
- Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA).
- Enhance performance and reliability of interface designs.
- Improve design quality across projects.
- Advance timing methodologies and best practices.
- Mentor and grow engineering talent.
- Foster collaboration and innovation.
- Strengthen Synopsys' reputation in AMS design.
- BS/MS in Electronics, Electromechanics, or Telecommunications.
- 5-8 years in analog/mixed signal or custom logic design.
- Basic understanding of timing analysis, SPICE simulation, and STA concepts.
- Scripting languages: Python, TCL for automation and data processing.
- Expertise in CMOS analog design and simulation tools.
- Proficiency with Cadence Virtuoso, SNSP tools, Hspice, Spectre.
- Strong English communication skills.
- Team player, supportive and responsible.
- Results-driven and enthusiastic about technology.
- Motivated mentor and problem solver.