
Design Verification Engineer - Principal
- Tp Hồ Chí Minh
- Lâu dài
- Toàn thời gian
- Develop and implement verification plans for read channel storage IP designs.
- Create and maintain testbenches using industry-standard verification tools and methodologies.
- Perform functional and performance verification of complex digital designs.
- Collaborate with design and architecture teams to identify and resolve design issues.
- Analyze and debug simulation failures and provide detailed reports on verification results.
- Mentor and guide junior verification engineers.
- BS/MS/PhD Degree in Electrical Engineering / Computer Engineering / Electronics and Telecommunications Engineering, or a related field.
- Proficiency in verification languages such as SystemVerilog, UVM, and scripting languages (Python, Perl, etc.).
- Understanding of ASIC design flow, strong understanding of digital design and verification methodologies.
- Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics).
- Strong mathematical skills.
- Experience with Digital Signal Processing (DSP) and knowledge of DSP modeling in C/C++.
- Strong problem-solving skills.
- Fluent in English language, excellent communication skills,
- Preferred Qualifications: Experience with high-speed DSP design verification.