Our client is a leading technology company who is looking for a qualified candidate to join their firm.Job description:Design and implement Design-for-Test (DFT) features to support automated test equipment (ATE), in-system testing, debugging, and diagnostics for silicon devices.Develop innovative DFT IP in collaboration with cross-functional teams, ensuring seamless integration of testability features into RTL at full-chip level.Partner with design, verification, and physical design teams to integrate, validate, and optimize test logic throughout all phases of design and back-end implementation.Perform timing analysis, interpret reports, and propose effective solutions to timing-related issues.Conduct gate-level simulations (with and without timing annotations) to validate functionality and robustness of DFT features.Diagnose and analyze silicon bring-up data logs, refine prototype patterns, and ensure test readiness.Drive DFT strategy and innovation for new silicon device models (including bare die and stacked die), establishing reusable methodologies for test and debug.Requirements6+ years of hands-on experience in DFT engineering.Strong understanding of DFT principles, clock architectures, and test methodologies.Proven experience with full-chip DFT flows, including Tessent Shell and hybrid vendor-tool flows.In-depth knowledge of industry standards: ATPG, JTAG, MBIST, and trade-offs between test quality, coverage, and time.Skilled in defining DFT specifications, driving DFT architecture, and applying advanced test strategies.Expertise in debugging compressed ATPG patterns, MBIST, and JTAG/IEEE 1500 issues.Proficient in creating and managing SDC timing constraints for SCAN, MBIST, and IJTAG test modes, with strong timing analysis capabilities.Familiarity with functional safety, clock-domain crossing (CDC) analysis, logic synthesis, and scan insertion.Contact: Giau Nguyen or Giang TranDue to the immense number of applications, only shortlisted candidates will be contacted.
