
Staff Engineer, Design Verification
- Đà Nẵng
- Lâu dài
- Toàn thời gian
- Analyze the and extract Spec, create comprehensive test plan and coverage plan.
- Contribute to the development of UVM components, ENV, Coverage model, and Assertion protocol checkers.
- Write testcases, run simulation, regression.
- Debug and propose bug fixings.
- Merge, analyze and improve the coverage results.
- Run GLN/SDF simulation and propose ECO fixings.
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 2-3 years of related professional experience, or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 1-2 years of experience.
- Experience with Verilog and SystemVerilog, preferably with UVM.
- Basic proficiency with C/C++.
- Experience with scripting languages, e.g., Python or Perl.
- Working knowledge of the Linux operating system.
- English Proficiency is a plus.