Digital IC Design, Staff Engineer (SYN/STA)
- Tp Hồ Chí Minh
- Lâu dài
- Toàn thời gian
- Perform logic synthesis at sub-system or top level for multi-million gate ASIC projects
- Perform ECO (Engineering-Change-Order) and formal verification
- Work with logic design and PnR engineers on logic, timing, power and physical issues.
- Manage schedules and support cross-functional engineering effort.
- Implement, enhance and maintain synthesis scripts.
- Contribute to the continuous development of IC design flow
- BS/MS in Electrical Engineering/Computer Engineering, or related fields and 6+ years of experiences working on logic synthesis for multi-million-gate ASIC/SoC projects. Newly graduated candidate with 7+ GPA is also welcome.
- Very familiar with IC design flow.
- Experiences in commercial implementation tools for logic synthesis (DC, Genus), formal verification (LEC, Formality), STA (PrimeTime, Tempus).
- Experience of synthesizable Verilog and/or VHDL codes.
- Experience in Linus environment and writing/using scripting languages such as Perl, TCL, etc.
- Knowledge of area, speed, power optimizations during logic synthesis.
- Self-motivated and excited to learn new skills, tools, IP, and design flows.
- Good written and oral communication skills in English.
- Experience in timing constraint development and timing constraint debug is a plus
- Experience in Conformal ECO flow, PnR tools is plus